1. Field of the Invention
The present invention relates to a semiconductor device and a method of manufacturing the semiconductor device.
2. Description of the Related Art
As information-oriented societies have rapidly developed, so has a demand to process massive information, which translates to a demand for a highly-integrated semiconductor device that is capable of rapidly transmitting data. However, it becomes increasingly difficult to provide ever more highly-integrated semiconductor devices with operational characteristics.
For example, polysilicon doped with impurities has been used for a conductive pattern such as a gate electrode and a bit line. However, the polysilicon has a specific resistance higher than that of a metal. Thus, when the polysilicon is used for the conductive pattern having a minute line width, the conductive pattern has a very high resistance which hinders the semiconductor device vis-à-vis achieving the required operational characteristics.
Further, to suppress a short channel effect due to a shortening of a gate length in a transistor, it is required to increase a concentration of impurities in a channel region. However, increasingly higher concentrations of impurities cause increasing occurrences of abnormal tunneling currents.
To overcome the above-mentioned problems, methods of forming a metal silicide layer on a polysilicon layer pattern as a gate electrode and source/drain regions have been studied in the Background Art. To form the metal silicide layer on the polysilicon layer and the source/drain regions, a metal layer is formed on the polysilicon layer pattern and the source/drain regions. A thermal treatment is then carried out to drive a reaction between a metal in the metal layer and silicon in the polysilicon layer pattern and the source/drain regions.
However, to reduce a resistance of the gate electrode, it is needed to form the metal silicide layer relatively thickly on the polysilicon layer pattern. The thick metal silicide layer expands into the channel region as well as the source/drain regions.
FIG. 1 is a cross sectional view illustrating a conventional transistor including a metal silicide layer pattern according to the Background Art.
Referring to FIG. 1, a conventional transistor includes a semiconductor substrate 10. A gate oxide layer 12 is formed on the semiconductor substrate 10. A polysilicon layer pattern 14 is formed on the gate oxide layer 12. A first metal silicide layer pattern 20 is formed on the polysilicon layer pattern 14. Spacers 16 are formed on sidewalls of the polysilicon layer pattern 14. Source/drain regions 18 are formed in the semiconductor substrate 10 at both sides of the polysilicon layer pattern 14. The source/drain regions 18 are silicidated to form a second metal silicide layer 22.
Here, when the source/drain regions 18 are excessively silicidated, the second metal silicide layer pattern 22 expands into a channel region A as well as the source/drain regions. An expanded portion of the second metal silicide layer pattern 22 causes an increased junction leakage current, a reduced punch-through margin, a reduced breakdown voltage, etc.
Further, it is required to prevent formation of a metal silicide layer pattern on a polysilicon layer pattern in a specific region of a semiconductor device. The specific region may correspond to a peripheral region where peripheral circuits for driving cells of the semiconductor devices are formed. Particularly, the specific region may correspond to a region where the polysilicon layer pattern is used as a resistive load.
Furthermore, transistors having characteristics and structures different from each other are formed in various regions of a semiconductor substrate by very complicated processes respectively. While the complicated processes are performed, process failures are frequently generated so that the semiconductor device has inferior operational characteristics.